1. Field of the Invention
The present invention relates to a MOS (Metal Oxide Semiconductor) device formed on an insulating film, and more specifically to a lower gate type thin film transistor.
2. Description of the Prior Art
A typical MOS transistor controls conduction of a channel located between a source and a drain in a field effect manner by exerting voltage on a gate electrode formed through an oxide film on the channel located between a source region and a drain region formed on a single crystal silicon substrate. In contrast, another MOS transistor called a lower gate type thin film transistor, controls conduction of a channel region formed on a gate electrode disposed on a silicon substrate via an oxide film or an insulating substrate the channel region being formed between a source region and a drain region formed via a gate insulating film, by exerting voltage on the foregoing gate electrode located below the channel region. The latter MOS transistor is used for SRAMs (Static Random Access Memory) and liquid crystal panel driving transistors.
Referring to FIG. 1, there is illustrated an arrangement of a prior art lower gate type thin film transistor. Fabrication of such a transistor is as follows. As illustrated in FIG. 1(a), a silicon oxide film 6 is formed on a silicon substrate 1 and thereafter a conductive film is deposited. The conductive film is a polycrystalline silicon film in which for example a proper impurity is doped at high concentration. The conductive film is patterned to form a lower gate electrode 21 on which a silicon oxide film is in turn deposited as a gate insulating film 7. On the gate insulating film 7 a thin polycrystalline silicon film 11 is deposited to form an active region.
For fabrication of the thin polycrystalline film 11, frequent use is made of a process wherein an amorphous silicon film is first deposited and heat-treated at about 600.degree. C. for a long time for polycrystallization. The polycrystalline silicon film 11 formed as such is ion-implanted locally into high concentration with impurity ion 41 with a photoresist film taken as a mask as illustrated in FIG. 1(b) for example to form a source region 22 and a drain region 26. On a masked portion of the polycrystalline silicon film 11 are formed a channel region 23 and an offset region 25. Thereafter, the impurily is activated with a heat treatment, and thus a basic structure of the illustrated lower gate type thin film transistor is formed. The resulting structure is called a lower gate type because of the provision of the gate electrode located below the active region. By reversing the fabrication order of the polycrystalline silicon film 11 as the active region and the gate electrode 21 an ordinary upper gate type thin film transistor can also be constructed.
The active region of the lower gate type field effect transistor constructed as described above comprises polycrystal which has a leakage current greater by three or more figures than that of single crystal silicon and further has an on-current lower by about four figures than that of the same. Prior practice to improve such difficulty includes heating (400.degree. C.) in the atmosphere of hydrogen and hydrogen plasma processing. However, a gate length is shortened as the device is integrated, and hence electric field intensity applied between a source and a drain is increased upon devices being switched off and further the allowable limit of a leakage current is lowered. To solve the difficulty there is adopted a method where an offset region is provided on the drain side of the channel part.
Resulting P channel transistor exhibits characteristics of 0.9 pA leakage current and a 60 nA on-current under the conditions of 1 .mu.m channel width and -3 V drain voltage. For applying the just-mentioned transistor to SRAMs (Static Random Memory) required to be fine and a high speed and to liquid crystal panel thin film transistors used at higher voltage, it is necessary to increase an on-current, decrease a leakage current, and make steep the driving of a drain current in gate voltage dependency.